A semiconductor foundry may provide standard cell libraries and design intellectual property (IP) blocks for integrated circuit (IC) designers. Standard cell libraries comprise a plurality of devices such as an inverter formed by a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor. Design IP blocks may comprise a variety of relatively complicated devices such as multiplexers, analog to digital (A/D) converters and the like. The devices in standard cell libraries and design IP blocks have been verified through various process characterization tests and data taken from the manufacturing line. Furthermore, standard cell libraries and design IP blocks may be integrated into leading electronic design automation (EDA) tools so that designers can reduce the rate of failure by complying with the design for manufacturing (DFM) rules in standard cell libraries and design IP blocks.
Both standard cell libraries and design IP blocks may comprise some metal oxide semiconductor (MOS) devices such as low-voltage n-type MOS devices modeled as a four-terminal device. However, when devices from standard cell libraries and design IP blocks are used in high voltage applications such as power management application, LCD driver application and the like, an n-type MOS device in high voltage applications may comprise a deep n-type well (DNW) formed between a p-type well and a p-type substrate. As a result, a pair of face-to-face diodes connected in series becomes a part of the n-type MOS device. The four-terminal MOS device model cannot be directly used to describe the electrical characteristics of the n-type MOS device comprising a pair of face-to-face diodes.
In the process of developing a new IC, a MOS device model may be used in various stages of designing the new IC such as a Simulation Program with Integrated Circuit Emphasis (SPICE) simulation stage, a Layout-Versus-Schematic (LVS) check stage or a Process Design Kit (PDK) design stage. As described above, the standard four-terminal MOS device model does not include the features of a MOS device having a special structure. Therefore, a model for multi-terminal MOS device is needed.
A dedicated multi-terminal MOS device model may be developed so that the extra terminals from the pair of face-to-face diodes can be included into the multi-terminal MOS device model. More particularly, the dedicated multi-terminal MOS device model may comprise all possible combinations in a foundry's semiconductor process. For example, there may be ten four-terminal models describing existing MOS devices provided by the foundry. The foundry may have six different types of deep n-type wells. In addition, each deep n-type well may have five different breakdown voltages. As a result, the total number of possible combinations of the above variations is 10 times 6 times 5, which comes to 300. In comparison to ten standard MOS device models provided by the foundry, the multi-terminal MOS device model approach may require extra support.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.